Communication between an image forming device and a replaceable supply item

ABSTRACT

A toner container installable in an image forming device having a controller according to one example embodiment includes a housing having a reservoir for storing toner. A chip is positioned on the housing and configured to receive a first write command from the controller of the image forming device. The chip is further configured to determine whether a transmission cycle bit of the first write command matches a transmission cycle bit of a second write command received by the chip from the controller of the image forming device previous to the first write command. The chip is further configured to resend to the controller of the image forming device a response to the second write command if the transmission cycle bit of the first write command matches the transmission cycle bit of the second write command.

CROSS REFERENCES TO RELATED APPLICATIONS

Divisional of U.S. patent application Ser. No. 15/951,586 filed on Apr.12, 2018.

BACKGROUND 1. Field of the Disclosure

The present disclosure relates generally to image forming devices andmore particularly to communication between an image forming device and areplaceable supply item.

2. Description of the Related Art

An electrophotographic image forming device typically includes one ormore customer replaceable supply items that have a shorter lifespan thanthe image forming device. For example, the image forming device mayinclude replaceable supply items that replenish the image formingdevice's toner supply and/or that replace worn imaging components, suchas the photoconductive drum, fuser, etc. It is desired for the imageforming device and the supply items to communicate information with eachother for proper operation. For example, it may be desired tocommunicate such information as authentication or validationinformation, consumption or usage rates, replacement schedules, etc.Each supply item typically includes a chip configured to communicatewith and respond to commands from a controller in the image formingdevice. Efficient communication between the controller of the imageforming device and the chips of the supply items is desired.

SUMMARY

A method of electrical communication between a slave node of an I2Ccommunication bus positioned on a replaceable supply item installed inan image forming device and a controller of the image forming device asa master node of the I2C communication bus according to one exampleembodiment includes receiving a first write command by the slave node onthe replaceable supply item from the controller of the image formingdevice. The slave node on the replaceable supply item compares a valueof a transmission cycle bit contained in a header of the first writecommand with a value of a transmission cycle bit contained in a headerof a second write command received by the slave node on the replaceablesupply item from the controller of the image forming device previous tothe first write command. If the value of the transmission cycle bitcontained in the header of the first write command is equal to the valueof the transmission cycle bit contained in the header of the secondwrite command, the slave node on the replaceable supply item sends tothe controller of the image forming device a response to the secondwrite command without executing the first write command.

A method of processing commands from a controller of an image formingdevice by a chip on a replaceable supply item installed in the imageforming device according to one example embodiment includes receiving awrite command by the chip on the replaceable supply item from thecontroller of the image forming device. The chip on the replaceablesupply item determines whether a transmission cycle bit of the receivedwrite command matches a transmission cycle bit of a preceding writecommand received by the chip on the replaceable supply item from thecontroller of the image forming device. If the transmission cycle bit ofthe received write command matches the transmission cycle bit of thepreceding write command, the chip on the replaceable supply item resendsto the controller of the image forming device a response to thepreceding write command upon receiving by the chip on the replaceablesupply item a read command from the controller of the image formingdevice corresponding to the received write command.

A method of facilitating electrical communication between a controllerof an image forming device and a chip for use on a replaceable supplyitem of the image forming device according to one example embodimentincludes configuring the chip to operate as a slave node on an I2Ccommunication bus where the controller of the image forming deviceserves as a master node on the I2C communication bus. The chip isconfigured to receive a first write command from the controller of theimage forming device, to determine whether a transmission cycle bit ofthe first write command matches a transmission cycle bit of a secondwrite command received by the chip from the controller of the imageforming device previous to the first write command, and to resend to thecontroller of the image forming device a response to the second writecommand if the transmission cycle bit of the first write command matchesthe transmission cycle bit of the second write command.

A toner container installable in an image forming device having acontroller according to one example embodiment includes a housing havinga reservoir for storing toner. A chip is positioned on the housing andconfigured to receive a first write command from the controller of theimage forming device. The chip is further configured to determinewhether a transmission cycle bit of the first write command matches atransmission cycle bit of a second write command received by the chipfrom the controller of the image forming device previous to the firstwrite command. The chip is further configured to resend to thecontroller of the image forming device a response to the second writecommand if the transmission cycle bit of the first write command matchesthe transmission cycle bit of the second write command.

A chip configured for communication with a controller of an imageforming device and mountable on a replaceable supply item forinstallation in the image forming device according to one exampleembodiment includes a processor and a memory. The memory stores programinstructions for execution by the processor including instructions toreceive a first write command from the controller of the image formingdevice, to compare a value of a transmission cycle bit contained in aheader of the first write command with a value of a transmission cyclebit contained in a header of a second write command received by theprocessor from the controller of the image forming device previous tothe first write command, and to send to the controller of the imageforming device a response to the second write command without executingthe first write command if the value of the transmission cycle bitcontained in the header of the first write command is equal to the valueof the transmission cycle bit contained in the header of the secondwrite command.

A chip for use on a replaceable supply item of an image forming deviceaccording to one example embodiment includes processing circuitryconfigured to communicate as a slave node of an I2C communication buswith a controller of the image forming device as a master node of theI2C communication bus. The processing circuitry is configured to receivea write command from the controller of the image forming device, todetermine whether a transmission cycle bit of the received write commandmatches a transmission cycle bit of a preceding write command receivedby the processing circuitry from the controller of the image formingdevice, and to resend to the controller of the image forming device aresponse to the preceding write command upon the processing circuitryreceiving a read command from the controller of the image forming devicecorresponding to the received write command if the transmission cyclebit of the received write command matches the transmission cycle bit ofthe preceding write command.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings incorporated in and forming a part of thespecification, illustrate several aspects of the present disclosure, andtogether with the description serve to explain the principles of thepresent disclosure.

FIG. 1 is a schematic view of an image forming device having one or morereplaceable supply items according to one example embodiment.

FIG. 2 is a block diagram depiction of the image forming deviceincluding a communication bus that permits communication between acontroller of the image forming device and one or more supply chipsaccording to one example embodiment.

FIG. 3 is a flowchart illustrating a method of issuing commands from thecontroller of the image forming device to a supply chip according to oneexample embodiment.

FIG. 4 is a flowchart illustrating a method of processing and respondingto commands received by the supply chip from the controller according toone example embodiment.

FIG. 5 is a flowchart illustrating a method of processing and respondingto commands received by the supply chip from the controller upon theoccurrence of a busy condition according to one example embodiment.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanyingdrawings where like numerals represent like elements. The embodimentsare described in sufficient detail to enable those skilled in the art topractice the present disclosure. It is to be understood that otherembodiments may be utilized and that process, electrical, and mechanicalchanges, etc., may be made without departing from the scope of thepresent disclosure. Examples merely typify possible variations. Portionsand features of sonic embodiments may be included in or substituted forthose of others. The following description, therefore, is not to betaken in a limiting sense and the scope of the present disclosure isdefined only by the appended claims and their equivalents.

Referring now to the drawings and particularly to FIG. 1, there is showna schematic depiction of an image forming device 10 according to oneexample embodiment. Image forming device 10 may include, for example, anelectrophotographic printer (commonly referred to as a laser printer),which may include scanning, copying or faxing functionality. One or moresupply items 100 are removably installed in image forming device 10allowing a user to replace or repair supply items 100 as needed in orderto continue printing. For example, FIG. 1 shows an access door 12 onimage forming device 10 that opens to allow a user to install or removesupply items 100 from image forming device 10. In the example embodimentillustrated, each supply item 100 includes a reservoir 102 formed withina housing 104 of the supply item 100 for holding a supply of toner foruse in print operations by image forming device 10.

However, supply item 100 may include any component requiring periodicuser replacement such as, for example, a fuser of an electrophotographicprinter, a waste toner container that stores unused toner removed from aphotoconductive drum or intermediate transfer member of anelectrophotographic printer, etc.

Each supply item 100 includes a supply chip 110 mounted on housing 104of the supply item 100. Supply chip 110 is electrically connected toelectrical contacts on supply item 100 that are positioned to mate withcorresponding electrical contacts in image forming device 10 when supplyitem 100 is installed in image forming device 10 in order to permitcommunication between supply chip 110 and a controller 20 of imageforming device 10. For example, supply chip 110 of supply item 100 andcontroller 20 of image forming device 10 may exchange authentication orvalidation information in order to ensure that supply item 100 isauthorized and suitable for use in image forming device 10. Supply chip110 of supply item 100 and controller 20 of image forming device 10 mayexchange operating or usage information such as an initial toner filllevel, an indication of a toner color contained within reservoir 104,ongoing toner supply levels, consumption or usage rates, replacementschedules, or other information useful for the operation of supply item100 in image forming device 10.

FIG. 2 shows a communication bus 30 of image forming device 10 thatfacilitates communication between controller 20 and supply chips 110according to one example embodiment. FIG. 2 shows one supply item 100and associated supply chip 110 in solid line and an additional supplyitem 100 n and associated supply chip 110 n in broken line indicatingthat additional supply items 100 having supply chips 110 may be used asdesired. In the example embodiment illustrated, communication bus 30utilizes the Inter-Integrated Circuit (I2C) protocol; however, othercommunication protocols may be used as desired. Controller 20 isconfigured to serve as the master node of communication bus 30 with eachsupply chip 110 configured to serve as a respective slave node. In theexample embodiment illustrated, a system chip 22 serves as an additionalslave node of communication bus 30. In this embodiment, controller 20and system chip 22 combine to form a control unit 24 of image formingdevice 10 that controls communication with supply chips 110. In oneembodiment, system chip 22 facilitates encrypted communication betweencontroller 20 and supply chips 110 where controller 20 and supply chips110 are unable to directly interpret messages from each other forsecurity purposes. For example, prior to sending an encrypted command toa supply chip 110, controller 20 may send the command to system chip 22which may decrypt and re-encrypt the command according to a format thatwill be understood by supply chip 110 and return the re-encryptedcommand to controller 20 to be sent by controller 20 to supply chip 110.Similarly, upon receiving an encrypted response from a supply chip 110,controller 20 may send the response to system chip 22 which may decryptand re-encrypt the response according to a format that will beunderstood by controller 20 and return the re-encrypted response tocontroller 20. System chip 22 may also aid controller 20 in theauthentication and validation of supply chips 110.

In the example embodiment illustrated, communication bus 30 includes abi-directional data line 32 that carries data back and forth betweencontroller 20 and the slave nodes and a clock line 34 that carries clocksignals from controller 20 to the slave nodes. Each slave node includesa respective address on communication bus 30 allowing controller 20 todirect communications to a particular slave node.

Controller 20, system chip 22 and supply chips 110 may each include aprinted circuit board assembly having one or more processors andassociated memory. The processor may include one or more integratedcircuits in the form of a microprocessor or microcontroller. The memorymay be any suitable combination of volatile and non-volatile memory suchas, for example, random access memory (RAM), read only memory (ROM),read-write memory, flash memory, EEPROM and/or non-volatile RAM (NVRAM).For example, controller 20 may include non-volatile memory storingprogram instructions for issuing commands to the slave nodes and forreceiving and processing responses from the slave nodes. Similarly,system chip 22 and supply chips 110 may each include non-volatile memorystoring program instructions for receiving and processing commands fromcontroller 20 and for responding to commands received from controller20. It will also be appreciated that various aspects of controller 20,system chip 22 and supply chips 110 may be implemented in specialpurpose hardware by way of one or more application-specific integratedcircuits (ASICs) such that the functions of controller 20, system chip22 and supply chip(s) 110 may be carried out by hardware, software or acombination thereof.

Controller 20 as the master node is programmed to issue various writeand read commands to the slave nodes over communication bus 30. Forexample, controller 20 may issue to commands to request authenticationor validation credentials from the slave nodes or to instruct the slavenodes to perform authentication or validation tests, to request tonercapacity or usage information from supply chips 110 or to store tonerusage information to supply chips 110, etc. In one embodiment, eachwrite command issued by controller 20 is followed by a correspondingread command from controller 20. Controller 20 initiates write and readcommands by sending a start condition over data line 32 of communicationbus 30 that includes the address of the intended slave node and aread/write bit set to a value representing either a write command or aread command. After initializing a write command, controller 20 sends adata packet associated with the write command to the receiving slavenode. After initializing a read command, controller 20 sends clockpulses on clock line 34 to the receiving slave node. The slave nodes areprogrammed to receive and process write commands from controller 20 andto send a response to controller 20 upon receiving the correspondingread command.

Commands and responses sent over communication bus 30 by the master nodand the slave nodes adhere to a particular data packet format allowingthe commands and responses to be understood by the receiving master nodeor slave node. For example, in one embodiment, each data packet includesa header that includes an indication of the length of the data beingtransmitted, an encryption bit that indicates whether or not the commandor response is encrypted and a transmission cycle bit that is toggledfor each new write command sent by controller 20 as discussed in greaterdetail below. Each write command transmitted by the master node alsoincludes a Command ID and each response transmitted by a slave nodeincludes a Response ED that allows the receiving slave node or masternode to identify the particular command or response being transmitted.Each data packet also includes the data being transmitted in the body ofthe data packet. In one embodiment, each data packet also includes acyclic redundancy check (CRC) value allowing the receiving master nodeor slave node to check the accuracy of the data transmitted as is knownin the art.

FIG. 3 illustrates a method 300 of issuing commands from controller 20as the master node to supply chip 110 as the slave node according to oneexample embodiment. At step 301, controller 20 sends a write commandover data line 32 of communication bus 30 to supply chip 110 with thetransmission cycle bit (tc) at an initial value (tc₀). At step 302,controller 20 sends a read command over data line 32 of communicationbus 30 to supply chip 110 and receives a response over data line 32 ofcommunication bus 30 from supply chip 110. At step 303, controller 20determines whether the response from supply chip 110 indicates thatsupply chip 110 calculated a CRC error indicating that an error occurredin the transmission of the write command from controller 20 to supplychip 110. If the response from supply chip 110 indicates that supplychip 110 calculated a CRC error, controller 20 resends the write commandto supply chip 110 at step 301 with the transmission cycle bit (tc) atthe initial value (tc₀) and sends a read command to supply chip 110 andreceives a response from supply chip 110 at step 302.

Resending the write command to supply chip 110 with the transmissioncycle bit (tc) at the initial value (tc₀) signals to supply chip 110that the write command received is a repeat of the preceding writecommand rather than a new write command. If the response from supplychip 110 indicates that supply chip 110 did not calculate a CRC error,controller 20 determines whether a CRC error is present in the responsereceived from supply chip 110 at step 304 indicating that an erroroccurred in the transmission of the response from supply chip 110 tocontroller 20. If the controller 20 determines that a CRC error ispresent in the response, controller 20 reseals the write command tosupply chip 110 at step 301 with the transmission cycle bit (tc) at theinitial value (tc₀) and sends a read command to supply chip 110 andreceives a response from supply chip 110 at step 302. Again, resendingthe write command to supply chip 110 with the transmission cycle bit(tc) at the initial value (tc₀) signals to supply chip 110 that thewrite command received is a repeat of the preceding write command ratherthan a new write command.

If controller 20 determines that no CRC error is present in theresponse, controller 20 determines whether the response from supply chip110 is encrypted at step 305. If the response from supply chip 110 isencrypted, controller 20 determines that the command was successful atstep 306 and toggles the transmission cycle hit (tc) from the initialstate (tc₀) to an opposite state (tc₁), i.e., controller 20 toggles thetransmission cycle bit (tc) from a binary zero state to a binary onestate or vice versa, at step 307. Toggling the transmission cycle bit(tc) at step 307 allows the next write command sent by controller 20 toinclude the transmission cycle bit at an initial value that is oppositethe initial value (tc₀) of the write command sent by controller 20 atstep 301. In this manner, the transmission cycle bit (tc) toggles backand forth between a binary zero state and a binary one state each time anew write command is sent signaling to supply chip 110 that the writecommand received is a new write command to be executed.

If the response from supply chip 110 is not encrypted, controller 20determines whether the response from supply chip 110 indicates thatsupply chip 110 is busy at step 308 indicating that controller 20 sentthe read command at step 302 before supply chip 110 finished executingthe write command sent at step 301. If the response from supply chip 110indicates that supply chip 110 is not busy, at step 309, controller 20compares a Command. ID value of the write command sent at step 301 witha Response ID value of the response received at step 302. If the CommandID value and the Response ID value match indicating that the responsereceived by controller 20 from supply chip 110 is responsive to thewrite command issued by controller 20, controller 20 determines that thecommand was successful at step 306 and toggles the transmission cyclebit (tc) from the initial state (tc₀) to an opposite state (tc₁) at step307. If the Command ID value and the Response ID value do not matchindicating that the response received by controller 20 from supply chip110 is not responsive to the write command issued by controller 20,controller 20 resets supply chip 110 at step 310 in order to attempt toresolve the error.

In one embodiment, if the response from supply chip 110 indicates thatsupply chip 110 is busy at step 308, controller 20 sends a “GetResponse” command over data line 32 of communication bus 30 to supplychip 110 with the transmission cycle bit (tc) at the initial value(tc₀). In the example embodiment illustrated, the Get Response commandis a special purpose command used only after a busy response is receivedfrom supply chip 110. The Get Response command instructs supply chip 110to provide a response to the last write command (other than anypreceding Get Response commands) received by supply chip 110. Thisallows controller 20 to continually poll supply chip 110 for a responsewhile supply chip 110 continues to execute the write command sent atstep 301 so that a response may be sent by supply chip 110 once supplychip 110 finishes executing the write command and is no longer in a busystate. The Get Response command allows controller 20 to continuallyrequest a response from supply chip 110 without having to reseal thefull write command each time. The Get Response command includes asmaller data packet and, in this manner, is abbreviated with respectedto other write commands sent by controller 20 to supply chip 110. As aresult, sending a Get Response command is typically more efficient thanresending the original write command.

FIG. 4 illustrates a method 400 of processing and responding to commandsreceived by supply chip 110 as the slave node from controller 20 as themaster node according to one example embodiment. At step 401, supplychip 110 receives a write command (Command_(n)) from controller 20 overdata line 32 of communication bus 30. At step 402, supply chip 110determines whether a CRC error is present indicating that an erroroccurred in the transmission of the write command from controller 20 tosupply chip 110. If supply chip 110 calculates a CRC error at step 402,upon receiving a read command over data line 32 of communication bus 30corresponding to the write command (Command_(n)) received at step 401,supply chip 110 sends an error response over data line 32 ofcommunication bus 30 to controller 20 at step 403 indicating that supplychip 110 calculated a CRC error. If supply chip 110 does not calculate aCRC error at step 402, supply chip 110 determines at step 404 whetherthe value of the transmission cycle bit (tc_(n)) contained in the writecommand (Command_(n)) received at step 401 is the same as the value ofthe transmission cycle bit (tc_(n-1)) contained in the preceding writecommand (Command_(n-1)) received by supply chip 110. If supply chip 110determines that the transmission cycle bit (tc_(n)) of the write command(Command_(n)) received at step 401 is not equal to the transmissioncycle bit (tc_(n-1)) of the preceding write command (Command_(n-1))received by supply chip 110 indicating that the write command(Command_(n)) received at step 401 is a new write command to beexecuted, at step 405, supply chip 110 executes the write command(Command_(n)) received at step 401. At step 406, upon receiving a readcommand corresponding to the write command (Command_(n)) received atstep 401, supply chip 110 sends a response over data line 32 ofcommunication bus 30 indicating the completion of the write command(Command_(n)) received at step 401.

If, on the other hand, supply chip 110 determines that the transmissioncycle bit (tc_(n)) of the write command (Command_(n)) received at step401 is equal to the transmission cycle bit (tc_(n-1)) of the precedingwrite command (Command_(n-1)) received by supply chip 110, supply chip110 determines at step 407 whether the Command ID value contained in thewrite command (Command_(n)) received at step 401 is the same as theCommand ID value contained in the preceding write command(Command_(n-1)) received by supply chip 110. If supply chip 110determines that the Command ID of the write command (Command_(n))received at step 401 is not equal to the Command ID of the precedingwrite command (Command_(n-1)) received by supply chip 110, in theexample embodiment illustrated, supply chip determines at step 408whether the Command ID value contained in the write command(Command_(n)) received at step 401 indicates that the write command(Command_(n)) is a Get Response command sent by controller 20 followinga busy response from supply chip 110 as discussed above. If supply chip110 determines that the write command (Command_(n)) is a Get Responsecommand, supply chip 110 proceeds to the method 500 illustrated in FIG.5 until the busy condition is resolved as discussed in greater detailbelow. If supply chip 110 determines that the write command(Command_(n)) is not a Get Response command, upon receiving a readcommand corresponding to the write command (Command_(n)) received atstep 401, supply chip 110 sends an error response to controller 20 overdata line 32 of communication bus 30 at step 403 due to the Command IDinconsistency.

If supply chip 110 determines that the Command ID of the write command(Command_(n)) received at step 401 is equal to the Command ID of thepreceding write command (Command_(n-1)) received by supply chip 110,supply chip 110 does not execute the write command (Command_(n))received at step 401 but instead, upon receiving a read commandcorresponding to the write command (Command_(n)) received at step 401,supply chip 110 simply resends the response to the preceding writecommand (Command_(n-1)) to controller 20 over data line 32 ofcommunication bus 30 at step 409. In this manner, the transmission cyclebit signals to supply chip 110 whether the write command (Command_(n))received at step 401 is a new write command to be executed or a repeatof the preceding write command (Command_(n-1)). The recognition bysupply chip 110 that the write command (Command_(n)) received at step401 is a repeat of the preceding write command (Command_(n-1)) improvesthe efficiency of supply chip 110 by allowing supply chip 110 to simplyreseed the response to the preceding write command (Command_(n-1))without executing the write command (Command_(n)) again. The recognitionby supply chip 110 that the write command (Command_(n)) received at step401 is a repeat of the preceding write command (Command_(n-1)) alsoprevents possible errors that could occur if supply chip 110 were toexecute the write commands (Command_(n-1, n)) twice instead of once asintended by controller 20.

If at any point after the receipt of the write command (Command_(n)) atstep 401 supply chip 110 receives the corresponding read command beforesupply chip 110 has completed processing the write command(Command_(n)), for example, prior to or during the execution of steps402, 404, 405, 407 or 408, supply chip 110 may send a busy response tocontroller 20 over data line 32 of communication bus 30. As discussedabove, the receipt of a busy response from supply chip 110 may causecontroller 20 to send a Get Response command to supply chip 110.

FIG. 5 illustrates a method 500 of processing and responding to commandsreceived by supply chip 110 as the slave node from controller 20 as themaster node after supply chip 110 issues a busy response to controller20 according to one example embodiment. At step 501, after previouslysending a busy response to controller 20, supply chip 110 receives a GetResponse command from controller 20 over data line 32 of communicationbus 30. If supply chip 110 is still busy processing the most recentwrite command (preceding the one or more Get Response commands received)upon receiving a read command from controller 20 corresponding to theGet Response command at step 502, supply chip 110 again sends a busyresponse to controller 20 over data line 32 of communication bus 30 atstep 503. Supply chip 110 may continue to receive additional GetResponse commands and send busy responses until supply chip finishesprocessing the most recent write command from controller 20. Once supplychip 110 completes processing the most recent write command at step 502,upon receiving a read command from controller 20, supply chip 110 sendsa response to the most recent write command received from controller 20.In this manner, the Get Response command accounts for the occurrence ofa busy condition of supply chip 110 allowing controller 20 tocontinually request a response from supply chip 110 without having toreseed the full write command each time.

While the example embodiments discussed above with respect to FIG. 3includes the issuing of commands from controller 20 as the master nodeto supply chip 110 as the slave node, the commands discussed in FIG. 3may instead to be issued by controller 20 as the master node to systemchip 22 as the slave node. Similarly, while the example embodimentsdiscussed above with respect to FIGS. 4 and 5 include the processing andresponding to commands received by supply chip 110 as the slave nodefrom controller 20 as the master node, the commands discussed in FIGS. 4and 5 may instead be received and processed by system chip 22 as theslave node from controller 20 as the master node.

The example embodiment discussed above include communications between acontroller 20 of an electrophotographic image forming device 10 and asupply chip 110 of a supply item 100 installed in image forming device10. The electrophotographic printing process is well known in the artand, therefore, is described briefly herein. During a print operation, acharge roll charges the surface of a photoconductive drum. The chargedsurface of the photoconductive drum is then selectively exposed to alaser light source to form an electrostatic latent image on thephotoconductive drum corresponding to the image being printed. Chargedtoner from a toner reservoir is transferred by a developer roll to thelatent image on the photoconductive drum creating a toned image. Thetoned image is then transferred from the photoconductive drum to theprint media either directly by the photoconductive drum or indirectly byan intermediate transfer member. A fusing unit fuses the toner to theprint media. A cleaning blade (or cleaning roll) removes any residualtoner adhering to the photoconductive drum after the toner istransferred to the print media. The cleaned surface of thephotoconductive drum is then ready to be charged again and exposed tothe laser light source to continue the printing cycle.

The foregoing description illustrates various aspects of the presentdisclosure. It is not intended to be exhaustive. Rather, it is chosen toillustrate the principles of the present disclosure and its practicalapplication to enable one of ordinary skill in the art to utilize thepresent disclosure, including its various modifications that naturallyfollow. All modifications and variations are contemplated within thescope of the present disclosure as determined by the appended claims.Relatively apparent modifications include combining one or more featuresof various embodiments with features of other embodiments.

1. A method of facilitating electrical communication between acontroller of an image forming device and a chip for use on areplaceable supply item of the image forming device, comprising:configuring the chip to operate as a slave node on an I2C communicationbus where the controller of the image forming device serves as a masternode on the I2C communication bus; and configuring the chip to receive afirst write command from the controller of the image forming device, todetermine whether a transmission cycle bit of the first write commandmatches a transmission cycle bit of a second write command received bythe chip from the controller of the image forming device previous to thefirst write command, and to resend to the controller of the imageforming device a response to the second write command if thetransmission cycle bit of the first write command matches thetransmission cycle bit of the second write command.
 2. The method ofclaim 1, further comprising configuring the chip to execute the firstwrite command and to send to the controller of the image forming devicea response to the first write command if the transmission cycle bit ofthe first write command does not match the transmission cycle bit of thesecond write command.
 3. The method of claim 1, further comprisingconfiguring the chip to determine whether a command ID of the firstwrite command matches a command ID of the second write command if thetransmission cycle bit of the first write command matches thetransmission cycle bit of the second write command and to perform saidresend to the controller of the image forming device the response to thesecond write command if the command ID of the first write commandmatches the command ID of the second write command.
 4. The method ofclaim 3, further comprising configuring the chip to send an errormessage to the controller of the image forming device if the command IDof the first write command does not match the command ID of the secondwrite command.
 5. The method of claim 3, wherein configuring the chip todetermine whether the command ID of the first write command matches thecommand ID of the second write command includes configuring the chip todetermine whether the command ID of the first write command indicatesthat the first write command is a request from the controller of theimage forming device for the chip to send a response to a most recentwrite command received by the chip from the controller of the imageforming device prior to the chip indicating a busy condition to thecontroller of the image forming device.